Resources Contact Us Home
High-speed domino logic circuit

Image Number 4 for United States Patent #6714059.

An improved high-speed domino logic circuit uses two delayed clock signals, CLKD and CLKDBAR, and three transistors to introduce a transition delay time. According to the invention, the delayed clock signals are used in conjunction with the three added transistors to avoid the contest or "fight" between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of improved high-speed domino logic circuit. The improved high-speed domino logic circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only three new transistors are required, the modification of the invention is space efficient and readily incorporated into existing designs.

  Recently Added Patents
Techniques for distributed storage aggregation
Module-code verification layer to automatically validate user input
Herbicide composition having improved effectiveness, method of preparation and use
Enhancement of semiconducting photovoltaic absorbers by the addition of alkali salts through solution coating techniques
Electronic communication device
Porous polymeric resins
Cleaning device, and image forming apparatus, process cartridge, and intermediate transfer unit each including the cleaning device
  Randomly Featured Patents
Methods for treating a patient undergoing chemotherapy
Methods and apparatus for focusing search results on the semantic web
Toner and method for producing toner
Systems and methods for network congestion management using radio access network congestion indicators
Semiconductor device and method of manufacturing the same
Substrate structures for integrated series connected photovoltaic arrays and process of manufacture of such arrays
Dispenser with safety locks
Paper container for fluid having spout plug