Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
High-speed domino logic circuit










Image Number 4 for United States Patent #6714059.

An improved high-speed domino logic circuit uses two delayed clock signals, CLKD and CLKDBAR, and three transistors to introduce a transition delay time. According to the invention, the delayed clock signals are used in conjunction with the three added transistors to avoid the contest or "fight" between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of improved high-speed domino logic circuit. The improved high-speed domino logic circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only three new transistors are required, the modification of the invention is space efficient and readily incorporated into existing designs.








 
 
  Recently Added Patents
Method for radiation sterilization of medical devices
Image correction method
Implantable neuro-stimulation electrode with fluid reservoir
Potato cultivar F10
Voltage detection apparatus and combination circuit
Method for counting and segmenting viral particles in an image
Inter vehicle communication system
  Randomly Featured Patents
Optical filter for a window
Tire for motorcycle
Devices, methods and software for generating indexing metatags in real time for a stream of digitally stored voice data
Method of cleaning boats that have been contaminated with oil and gas well drilling fluids and hazardous waste
Vented reclosable bag
End to end walking print
Semiconductor memory circuit
Chip-type light emitting device having precisely coated wavelength-converting layer and packaged structure thereof
Mobile host using a virtual single account client and server system for network access and management
Injector tip cleaning systems and methods