Resources Contact Us Home
High-speed domino logic circuit

Image Number 4 for United States Patent #6714059.

An improved high-speed domino logic circuit uses two delayed clock signals, CLKD and CLKDBAR, and three transistors to introduce a transition delay time. According to the invention, the delayed clock signals are used in conjunction with the three added transistors to avoid the contest or "fight" between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of improved high-speed domino logic circuit. The improved high-speed domino logic circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only three new transistors are required, the modification of the invention is space efficient and readily incorporated into existing designs.

  Recently Added Patents
Continuously variable transmission and control method thereof
Pre-distortion architecture for compensating non-linear effects
Method and system for automatically hiding irrelevant parts of hierarchical structures in computer user interfaces
Semiconductor device and fabrication method
Treatment of cancer using the sodium salt of a benzoic acid derivative
Backside structure and methods for BSI image sensors
Vertical gate LDMOS device
  Randomly Featured Patents
Method of characterizing the flowpath for fluid injected into a subterranean formation
Variable offset amplifier circuits and their applications
Automatic evolution of mixed analog and digital electronic circuits
Method and system for controlling a call handover between telecommunication networks
Television stand
Improved continuous low fluid exchange water heater
Use of an oxide ceramic material for compression molds for shaping elements made from glass or a glass-containing ceramic and having high surface quality and dimensional accuracy
Particle concentrating sampler
Oscillator voltage regulator
Low power LCD driving scheme employing two or more power supplies