Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
High-speed domino logic circuit










Image Number 4 for United States Patent #6714059.

An improved high-speed domino logic circuit uses two delayed clock signals, CLKD and CLKDBAR, and three transistors to introduce a transition delay time. According to the invention, the delayed clock signals are used in conjunction with the three added transistors to avoid the contest or "fight" between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of improved high-speed domino logic circuit. The improved high-speed domino logic circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only three new transistors are required, the modification of the invention is space efficient and readily incorporated into existing designs.








 
 
  Recently Added Patents
Harmonic sensor
Plasma panel based radiation detector
Shot scent dispenser
Laminar library screen
Computer network running a distributed application
Cooler
Isolated SCR ESD device
  Randomly Featured Patents
Method to enhance an immune response of nucleic acid vaccination
Apparatus for optional straight or directional drilling underground formations
Electronic equipment and power management method for the electronic equipment, and power source unit
Variably insulated blanket
Constant current density high voltage power supply
Method and system for embedding an aggregated event stream into a third party web page
Battery pack
Drier for temperature sensitive materials
Defining and executing processes using declarative programming language constructs
Pattern transfer method and imprint device