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Differential latch and applications thereof










Image Number 8 for United States Patent #6693476.

A differential latch includes a sample transistor section, a hold transistor section, a 1.sup.st gating circuit and a 2.sup.nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., V.sub.DD and V.sub.SS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1.sup.st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1.sup.st clocking logic operation and a 2.sup.nd clocking logic operation. The 2.sup.nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3.sup.rd clocking logic operation and a 4.sup.th clocking logic operation.








 
 
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