Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Highly-integrated flash memory and mask ROM array architecture










Image Number 2 for United States Patent #6687154.

A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.








 
 
  Recently Added Patents
Integrated transmit/receive switch
High pressure refolding of protein aggregates and inclusion bodies
Chemical method of making a suspension, emulsion or dispersion of pyrithione particles
Methods and systems for managing electronic messages
Light emitting device
Alterable account number
Cathode active material and lithium secondary battery comprising the same
  Randomly Featured Patents
Oil return for reduced height scroll compressor
7-16 coaxial flanged receptacles
Systems and methods for detecting obstructions in a camera field of view
Iontophoretic delivery of rotigotine for the treatment of Parkinson's disease
Controller for computer printing system
Optical arrangement with a spectrally selective element
Method and apparatus for marking on an arcuate surface
Method of producing a coupling element for an optical transmission fiber
Method and apparatus for predictive flash memory erase and write times
Fecal occult test packaging