Resources Contact Us Home
Highly-integrated flash memory and mask ROM array architecture

Image Number 2 for United States Patent #6687154.

A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.

  Recently Added Patents
Portable hand-held multi-function device for storing, managing and combining rewards
Meat-containing, strip shaped food product and method of making same
Method and apparatus for verifiable generation of public keys
Method for releasing a locking in mobile terminal and mobile terminal using the same
Integrated emergency medical database system
Image forming apparatus, control method, and storage medium
  Randomly Featured Patents
Sensor and diverter mechanism for an image forming apparatus
Polyolefin-based nanocomposite and preparation thereof
Colloid relief images by oxidized developer transfer
Nonlinear via arrays for resistors to reduce systematic circuit offsets
Closed compression--type coaxial cable connector
High data rate digital demodulator and bit synchronizer
Storage device for tools, especially screwdriver bits
Method for performing gate coordination on a per-call basis
Disk cartridge for disk player with integrated disk changer
Information processing system having microprogram-controlled type arithmetic processing unit