Resources Contact Us Home
Highly-integrated flash memory and mask ROM array architecture

Image Number 2 for United States Patent #6687154.

A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.

  Recently Added Patents
Image display device and display unit for image display device
Implant free extremely thin semiconductor devices
System and method for solving connection violations
Nickel-cobalt-manganese multi-element lithium ion battery cathode material with dopants and its methods of preparation
Method for manufacturing non-volatile memory device, non-volatile memory element, and non-volatile memory device
Organic electroluminescence element
Refuelable battery-powered electric vehicle
  Randomly Featured Patents
Integrated vehicle engine/transmission control apparatus
Preparing glass compositions using a fayalite iron source
Protection vest
Device for testing smart card and method of testing the smart card
Driving hub for a wheel-mounted decorative member
Exposure control apparatus for camera with shake countermeasure
Supercharging arrangement for the charge air of an internal combustion engine
Hard drive authentication
Quinazoline derivatives as NK3 receptor antagonists
Elution method and device