Resources Contact Us Home
Highly-integrated flash memory and mask ROM array architecture

Image Number 2 for United States Patent #6687154.

A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.

  Recently Added Patents
Sealing member for piezoelectric resonator device, and piezoelectric resonator device
Adding value to a rendered document
Luggage cart
Bipolar transistor with diffused layer between deep trench sidewall and collector diffused layer
Cake knife handle
Metal-doped oxide, method of preparing the same, and solid oxide electrolyte using the metal-doped oxide
Multi-band dipole antenna
  Randomly Featured Patents
Virtual channel table for a broadcast protocol and method of broadcasting and receiving broadcast signals using the same
System and method for programming and controlling over current trip point limits in voltage regulators
Topsheet pattern for a sanitary napkin
Apparatus for measuring the waviness of a workpiece surface
Apparatus for removing and collecting moisture from a moisture-laden air flow
Method and system for simulated interactive conversation
Automobile trunk organizer
Piping for the completion of a groundwater monitoring site
Automated screener
Operating unit and stove