Image Number 7 for United States Patent #6653732.
An electronic component includes a semiconductor chip and/or a test structure. The semiconductor chip includes a multi-layer coating having at least one interconnect layer, at least one insulation layer, and at least one planarization layer. A method of producing the component is also disclosed. Embedded adhesion regions are provided in the planarization layer, whereby the adhesion regions provide adhesion surfaces to the adjacent insulation layers.