Resources Contact Us Home
Set of three level concurrent word line bias conditions for a nor type flash memory array

Image Number 19 for United States Patent #6620682.

In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

  Recently Added Patents
Portable electronic device housing including hinge
Output circuit
Method and apparatus for monitoring wireless communication in hearing assistance systems
Thermally efficient busway
Shape memory polymers formed by self-crosslinking of copolymers
  Randomly Featured Patents
Image sensing apparatus cleaning operation and control method of said cleaning operation
Small form-factor pluggable cage assembly
Thonged hosiery garment
Aqueous polish composition
Magnetic toner
Napkin dispenser
Recessed hinge to make the temples of spectacles elastic
Magnetic powder, permanent magnet produced therefrom and process for producing them
Power unit for a two-wheeled vehicle
Rotary position transducer