Image Number 8 for United States Patent #6594741.
A system and method are presented for a write buffer that combines capabilities and features implemented in separate, specialized buffers in prior art microprocessors. The write buffer receives data records from a CPU and subsequently transfers them to a memory bus. In addition to the data records themselves, each location in the buffer contains a complement of control bits, which determine the mode in which the associated record will be transferred to the memory bus. The use of these bits allows the buffer to perform memory transfers associated with a write-back data cache or an EJTAG test module, as well as more conventional transfers traditionally performed by a write buffer. The combination of these multiple capabilities in a single write buffer is believed to simplify the design of the bus interface unit in a microprocessor incorporating the principles disclosed herein.