Image Number 10 for United States Patent #6579778.
A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating gates above the channel regions and polysilicon word lines. The Vss Bus is then formed by etching away portions of the field oxide between corresponding source regions of adjacent bit lines to expose portions of the substrate, ion implanting impurities into the source regions and the exposed substrate, forming insulating spacers on the sides of the floating gates and word lines, and forming a metal silicide layer, such as titanium silicide, on the implanted source regions and exposed portions of the substrate to form a continuous conductor between the source regions. The metal silicide layer provides a low-resistance Vss, thereby improving device performance, while the implanted impurities ensure that the substrate will not short circuit to source and drain regions through the metal silicide.