Resources Contact Us Home
Designing integrated circuits to reduce electromigration effects

Image Number 3 for United States Patent #6578178.

A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.

  Recently Added Patents
Wafer level packaging
Method and system for selecting a target with respect to a behavior in a population of communicating entities
Single-chain variable fragment (scFv) able to recognize and bind CD99 human protein
Event handling in an integrated execution environment
Controller for soldering iron
Pear-shaped convertible reading glasses
Image stabilization apparatus and image pickup apparatus
  Randomly Featured Patents
Low temperature bleaching with positive bromine ions (Br.sup.+)
Modular connector system having electrical and optical links
Method for forming paper boxes and the like
Image reading apparatus and drive control method thereof
Multi-level pulse amplitude modulation receiver
Image retrieval system
Bunsen burner guard
Solar cells
Anti-twist electrical wiring to a plug
Method and apparatus for setting a voltage controlled crystal oscillator in a video processing device