Resources Contact Us Home
Restricting the damaging effects of software faults on test and configuration circuitry

Image Number 4 for United States Patent #6578166.

A system that restricts the damaging effects of software faults that interact with test and configuration circuitry. This test and configuration circuitry includes a scan chain in the form of a serial linkage between memory elements within a circuit, thereby allowing a test input to be serially shifted into the memory elements. The system operates by receiving a test disable signal at the circuit. In response to the test disable signal, the system moves the circuit into a test disable mode, which limits any damaging effects to the circuit caused by shifting the test input into the memory elements in the scan chain. Next, the system shifts the test input into the memory elements in the scan chain. T he system also determines whether the test input will cause damage to the circuit after the test input is completely shifted into the scan chain. If so, the system holds the circuit in the test disable mode so that the test input cannot damage the circuit. If not, the system moves the circuit out of test disable mode, and runs the circuit for at least one clock cycle in order to test the circuit.

  Recently Added Patents
Zoom lens
Case for electronic device
Mobile application for calendar sharing and scheduling
Calibration of quadrature imbalances using wideband signals
Stack and folding-typed electrode assembly and method for preparation of the same
Semiconductor device including multi-chip
Charged particle beam apparatus
  Randomly Featured Patents
Natural gas engine lubricating oil compositions
Herbicidal 2-alkyl glycerol derivatives
Flow control system for network devices
Clip-type friction hinge device
Quality regulating apparatus and method
Multi-band antennas using multiple parasitic coupling elements and wireless devices using the same
Digital camera
Reed opener assembly
Apparatus, system, and method for cross-system proxy-based task offloading
Virtual high density programmable integrated circuit having addressable shared memory cells