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Non-volatile ferroelectric capacitor memory circuit having nondestructive read capability

Image Number 3 for United States Patent #6574134.

A non-destructive ferroelectric capacitor-based memory circuit has a plurality of word lines located in parallel to each other. A plurality of bit lines is located across the word lines and a plurality of memory cells is located at intersections between the word lines and the bit lines. Each of the memory cells further has a MOS transistor and two ferroelectric capacitors coupled together in series to have a common node to couple with the transistor, and two plate lines coupled with two non-common nodes of the two series ferroelectric capacitors, respectively.

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