Resources Contact Us Home
Method to reduce power bus transients in synchronous integrated circuits

Image Number 3 for United States Patent #6559701.

A method of reducing power rail transients on integrated circuits. The power rail transients are reduced by controlling clock skew in a manner which minimizes dI/dT current demands. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out the number of simultaneous switching elements. By controlling the number of simultaneous switching devices, a significant reduction in time rate of current demanded from the power rails can be achieved, thereby reducing the magnitude of V.sub.SS /V.sub.DD voltage transients due to parasitic inductances and resistances supplying power to the integrated circuit. Theoretically, the entire timing spread of the slack graph for clock skew can be used to control the number of simultaneous switching devices.

  Recently Added Patents
Methods for testing OData services
Image processing apparatus, image display apparatus, and image processing method
Method of manufacturing semiconductor device
Phase noise extraction apparatus and technique
Centralized behavioral information system
Polynucleotide capture materials, and methods of using same
Systems and methods for cryopreservation of cells
  Randomly Featured Patents
Image forming apparatus
Drop controller
Method of making field-effect transistors with micron and submicron gate lengths
Debris deflecting device
Glove-like dynamic splint and method of using same
Processing apparatus with conveying unit for continuously conveying heat pipes
Comparator mask for aperture measuring apparatus
Attachment for a bat
DNA cassettes for expression of lytic peptides in mammalian cells and transgenic organisms containing same
Methods for treating IFN-.gamma. mediated diseases using human anti-IFN-.gamma. neutralizing antibodies as selective IFN-gamma pathway inhibitors