Resources Contact Us Home
Timing circuit and method for a compilable DRAM

Image Number 4 for United States Patent #6538932.

A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.

  Recently Added Patents
Laminar library screen
Method for treating wounds for mammals, wound healer compound, and method of manufacturing thereof
Methods and systems providing desktop search capability to software application
Mobile terminal and method for changing page thereof
Intake parameter-calculating device for internal combustion engine and method of calculating intake parameter
Harmonic sensor
Diagnostic data interchange
  Randomly Featured Patents
Solenoid plunger magnet and its use as print hammer in a print hammer device
Electric motor
Medical instrument holding apparatus
Two-beam semiconductor laser device
Trailer light harness storage and protector caddy
Semiconductor light emitting module and method for manufacturing the same
Oxygen-resistant electroconductive carbon bodies
Airborne obstacle collision avoidance apparatus
One-way shaking switch
Roll with composite coats