Resources Contact Us Home
Timing circuit and method for a compilable DRAM

Image Number 4 for United States Patent #6538932.

A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.

  Recently Added Patents
Method and system for providing intelligent call rejection and call rollover in a data network
Organic light-emitting display and method of manufacturing the same
Method for transferring inventory between virtual universes
Correlating trace data streams
Sitagliptin intermediate compounds, preparation methods and uses thereof
Multi-contoured yoga support
System and method for creating a build set and bill of materials from a master source model
  Randomly Featured Patents
Combination of slide members
LGA compression contact repair system
Dashboard and console for an automobile
Multi-volume audit trails for fault tolerant computers
Cellular pager
Closure cap for a bottle of like containers
Filter apparatus
Method and apparatus for customizing cigarette packages
Scleroglucan as a rheological modifier for thermal insulation fluids
Signaling for wireless communications