Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Timing circuit and method for a compilable DRAM










Image Number 4 for United States Patent #6538932.

A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.








 
 
  Recently Added Patents
Process to increase selectivity to ethylene in oxygenates-to-olefins conversions
Crowd control barrier II
Display screen with graphical user interface
Valved, microwell cell-culture device and method
Headset systems and methods
Method and apparatus for policy-based network access control with arbitrary network access control frameworks
Crystalline form of zofenopril calcium
  Randomly Featured Patents
Piston crankshaft connecting rod
Circular ring shaped brush section for sweeping machine
Spinning ring
Imaging system for a multi-magnification copier utilizing gradient index lens array
Showerhead
Tetrahydroindole derivatives for treatment of alzheimer's disease
Delivery system and manifold
Passivation of multi-layer mirror for extreme ultraviolet lithography
Compositions useful in copper oxidation, and a method to prepare copper oxidation solutions
Process for preparing fine powder of silk fibroin