Resources Contact Us Home
Timing circuit and method for a compilable DRAM

Image Number 4 for United States Patent #6538932.

A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.

  Recently Added Patents
Monolithic widely-tunable coherent receiver
Sending notification of event
Lead frame array package with flip chip die attach
Image processing apparatus, image processing method, and program
Push mechanism for efficiently sending aggregated data items to client
Hybrid fiber constructions to mitigate creep in composites
Headset electronics
  Randomly Featured Patents
Stuffed rabbit figure
Wireless medical gases management system
PLL circuit
Battery frame and battery
Dark field inspection system
Process for the work-up of complex amine hydrofluroides
Ceramic superconducting composition and process and apparatus for preparing thereof
Floating idler pulley retard system for mixed mail separation
Surface emitting laser with an integrated absorber
Zone-based optimization framework for performing timing and design rule optimization