Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Timing circuit and method for a compilable DRAM










Image Number 4 for United States Patent #6538932.

A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.








 
 
  Recently Added Patents
Touch screen panel
Stool
Method of forming a semiconductor package
Analog-to-digital converter with input voltage biasing DC level of resonant oscillator
Electrical terminal
Image processing apparatus capable of using replacement component, image forming apparatus capable of using replacement component, and method of administrating replacement component
Case for electronic device
  Randomly Featured Patents
Echo controlling apparatus of video conferencing system and control method using the same
Portable spray system
Rolling machine for paper arts
Optical deflector and optical device
Insulative shield, particularly for automotive exhaust components
Toy fire fighting display
Model of the contact region of integrated circuit resistors
Device for tensioning of a pulling element of a printer
Elastomeric interpolymer blends
Reconfigurable array to compute digital algorithms