Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Arrangement relating to electronic circuitry










Image Number 3 for United States Patent #6501181.

The present invention relates to an arrangement in a multilayered electronic circuit. In a transition between two planar transmission lines, a compensating element is used to keep the average capacitance per length unit more constant during the transition. A via conductor the passes near an edge of a planar conductor pattern, the via conductor and the planar conductor having a mutual capacitive coupling within a predetermined range. A compensating conductor is formed between the planar conductor and the via conductor, which conductor is connected to the planar conductor by a compensating via. If the segment of the via conductor which belongs to the same via hole pattern as the compensating via is displaced, the compensating via is also displaced. The compensating planar pattern is then disconnected from the planar conductor. This improves yield in a given multilayer process.








 
 
  Recently Added Patents
Systems and methods for detecting and rejecting defective absorbent articles from a converting line
Display screen with graphical user interface
Triazine ring-containing polymer and film-forming composition comprising same
Laminar library screen
Remote device pairing setup
Probiotic enriched and low organic acid food products
Implant for performance enhancement of selected transistors in an integrated circuit
  Randomly Featured Patents
Band-pass filter having three or more loop-shaped electrodes
Dial signal generator for generating dial pulse signal and dual tone multi-frequency signal
Retention mechanism for self-securement of ZIF PGA socket
Halftone phase shift photomask and blank for halftone phase shift photomask
Strain gauge with resonant light modulator
Asphalt plant control house
Bottle opener
Method and apparatus for manufacturing ink jet recording head
Circuit for driving flat panel display
Generating and displaying an application flow diagram that maps business transactions for application performance engineering