Image Number 3 for United States Patent #6462982.
A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell has a magnetoresistance element and a switching element which establishes a connection between a corresponding sense line and the magnetoresistance element when a corresponding word line is addressed. A number of sense circuits are respectively provided for the sense lines. Each sense circuit includes a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and causing it to discharge when the corresponding sense line is addressed. The voltage developed across the capacitive element of each sense circuit is used to produce a binary output signal representative of information stored in an address memory cell. A number of voltage control elements are provided for maintaining the sense lines at constant lower voltages regardless of higher voltages produced by the sense circuits.