Resources Contact Us Home
Process for fabricating a aligned LDD transistor

Image Number 3 for United States Patent #6436776.

A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.

  Recently Added Patents
Load balancing for parallel tasks
Battery comprising circuitry for charge and discharge control, and method of operating a battery
Haloalky -substituted amides as insecticides and acaricides
Sensor system
Blended block copolymer composition
Device having built-in digital data device and light for insertion into a lamp holder
Efficient forward ranking in a search engine
  Randomly Featured Patents
Polysaccharide RBS substance and antitumor agent containing same
Adjustable wrench
Air-conditioning system for electronic components
Tab molecules
Technique to suppress bitline leakage current
Arrangement for coupling optional auxiliary devices to terminal equipment of private branch exchanges
Integrated resource management system and method
Moisture-retentive cooling gel, moisture-retentive cooling gel laminate, and moisture-retentive cooling plaster
Touch screen for mobile telephone