Resources Contact Us Home
Process for fabricating a aligned LDD transistor

Image Number 11 for United States Patent #6436776.

A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.

  Recently Added Patents
System and method for text input with a multi-touch screen
Method for carrying out a chemical reaction
Normalized contextual performance metric for the assessment of fatigue-related incidents
Business card assembly
Graphical planner
Segmenting video based on timestamps in comments
Triple-action pest control formulation and method
  Randomly Featured Patents
Valve timing controller
Antiviral agents
Elevator stop control arrangement
Input device using tapping sound detection
Corner brace
Therapeutic use of multilamellar liposomal prostaglandin formulations
Ground stabilizing equipment
BRAF mutations conferring resistance to BRAF inhibitors
Method and apparatus for antenna diversity
Method and system for pre-drill pore pressure prediction