Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Process for fabricating a aligned LDD transistor










Image Number 10 for United States Patent #6436776.

A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.








 
 
  Recently Added Patents
Stage drive method and stage unit, exposure apparatus, and device manufacturing method
Method of optimizing air mover performance characteristics to minimize temperature variations in a computing system enclosure
Oil extractor and the preparation method thereof
White light emitting lamp and white LED lighting apparatus including the same
Focus information generating device and focus information generating method
Method and system for fail-safe call survival
Deflection device for a scanner with Lissajous scanning
  Randomly Featured Patents
Real time lockdown
Ground plane shield
Parallel triangle tessellation
Machine especially for harvesting leaf vegetables
Cosmetic compositions containing rosemary extract and DHA
Method of processing mass air sensor signals
Method for growing crystals
Silico-titanates and their methods of making and using
Journal bearing for a carrier for paper rolls
Freeze-dried product for introducing nucleic acid, oligonucleic acid or derivative thereof