Resources Contact Us Home
Delay locked loop for use in semiconductor memory device

Image Number 3 for United States Patent #6434062.

It is provided a delay locked loop for obtaining a reduced jitter and a stable time delay adjustment to thereby perform a bi-directional time delay with a small area even at low frequency applications. The delay locked loop includes an input unit for receiving a clock signal and a non-clock signal and comparing received signals to produce an internal clock signal, a controller for receiving the internal clock to produce a control signal, a bi-directional oscillator, responsive to the control signal from the control means, for performing a ring oscillation in a first or second direction and fulfilling an addition and subtraction adjustment function for a time delay, a counter for receiving an output signal of the bi-directional oscillator and counting the number that the signal is passed therethrough, and an AND gate for performing a combination operation on the outputs of the bi-directional oscillating means and the counting means, to produce the result as a final internal clock signal.

  Recently Added Patents
Method for manufacturing a magnet coil configuration using a slit band-shaped conductor
Structure of circuit board and method for fabricating the same
Data processor and scanner device
Lubricating oil compositions
Method of operating an electromechanical converter, a controller and a computer program product
Bull stationery tab
  Randomly Featured Patents
GABA and L-glutamic acid analogs for antiseizure treatment
Method of activating boron nitride
Malleable penile prosthesis
Waterproof press-connecting connector
Massaging device
Membrane separation of hydrocarbons using cycloparaffinic solvents
Fuel container
Starting pitches for carbon fibers
Method and apparatus for workgroup information replication
Mobile phone