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Multiboard run-in tester for PCI expansions

Image Number 3 for United States Patent #6414505.

A system for running in, in which multiple PCI bus connections are each bridged to multiple boards-under-test. The presence or absence of power in each of these bus connections is monitored, and the boards-under-test are correspondingly powered up (or not). Multiple test-bed subboards are preferably used, each with multiple sockets for receiving boards-under-test with high-insertion-force connectors, and the independent power control permits the boards-under-test on one subboard to be powered off and swapped while the boards-under-test on the other subboard are still being exercised. Preferable a single movable extractor mechanism is mounted on each subboard, and can be positioned (with respect to any one of the high-insertion-force connectors) for linear extraction of the board-under-test without any torque.

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