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Semiconductor memory having parallel test mode










Image Number 4 for United States Patent #6400623.

A semiconductor memory (200) having a plurality of banks (10 and 20) of memory cells in which a parallel test operation can allow bits from each bank to be tested in parallel. According to one embodiment, the semiconductor memory may include a data amplifier (30) having a selection circuit (110), data sense circuit (120), data output circuit (130), control circuit (140), and comparator (C1). In a normal mode of operation, the selection circuit (110) may be coupled to receive I/O busses (IOAT/N and IOBT/N) from memory banks (10 and 20) and based on selection control signals (TR1 to TR4), may select data to be amplified by data sense circuit (120) and output to a read/write bus RWBST/N. In a test mode of operation, the selection circuit (110) may be coupled to receive I/O busses (IOAT/N and IOBT/N) from memory banks (10 and 20) and may couple data from each memory bank (10 and 20) to a data sense circuit (120) to be amplified and applied to comparator (C1). Comparator (C1) may compare the data in parallel and output a comparison result to read/write bus RWBST/N. In this manner a data amplifier (30) may be shared by a plurality of banks (10 and 20) and also provide parallel test operation.








 
 
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