Image Number 3 for United States Patent #6385712.
A method and apparatus for segregation of virtual address space in a computer system is provided. An embodiment of the invention provides compatibility of an emulated processor architecture with a native processor architecture. Address space for the emulated processor architecture is provided and segregated from other address space, such as address space designated for use by a native processor, where the native processor is the processor actually present in a computer system. An embodiment of the invention provides separate exception handlers to handle translation lookaside buffer (TLB) misses for each address space. An embodiment of the invention provides an address space tag associated with a virtual address to designate the address space to which that virtual address pertains.