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Field-effect transistor having a high packing density and method for fabricating it










Image Number 3 for United States Patent #6384456.

A field-effect transistor has a semiconductor body with a main area, in which at least one source zone and one drain zone are introduced and which is provided with a gate electrode isolated from a channel region disposed between a source zone and a drain zone by an insulator layer. In the field-effect transistor, the source zone, the drain zone and the channel region are disposed in walls of a respective trench or recess formed in the semiconductor body.








 
 
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