Image Number 4 for United States Patent #6376308.
A process for fabricating an EEPROM device having pocket substrate regions includes forming a pattern composite layer overlying a principal surface of a semiconductor substrate. The pattern composite layer includes a dielectric layer and a resist layer overlying the dielectric layer. Processing is carried out to reduce the lateral dimension of the resist layer relative to the dielectric layer thereby exposing an upper surface of the dielectric layer. A doping process is carried out in which dopants penetrate the exposed upper surface of the dielectric layer and enter the semiconductor substrate immediately below the exposed upper surface of the dielectric layer. Upon conforming the pocket regions, an oxidation process is carried out to form bit-line oxide regions in the semiconductor substrate.