Resources Contact Us Home
Clock tree topology

Image Number 3 for United States Patent #6353352.

A clock tree topology distributes a clock signal from a single input terminal 400 to three terminals 421-423 with an equal phase delay. The topology includes four lines 401-404 connected together at a first end 450 with adjacent lines forming right angles. A second end of the line 404 forms the clock signal input terminal 400. A second end of the remaining lines 401-403 are connected to first ends of lines 411-413. Second ends of the lines 411-413 form the terminals 421-423. A right angle is formed between each of the lines 401-403 and the respective one of the lines 411-413 to which it connects.

  Recently Added Patents
Metal-containing compositions and method of making same
Determination of copy number variations using binomial probability calculations
Apparatus and method for recording reboot reason of equipment
Compositions and methods for producing isoprene
White light emitting diode (LED) lighting device
Electronic device with multi-orientation
Semiconductor device
  Randomly Featured Patents
Printing system and method thereof
Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same
Hairbrush handle
Side dump body having an increased carrying capacity
Device for calculating the moments of image data
Input buffer circuit including an input level translator with sleep function
Longitudinally coupled surface acoustic wave resonator filter
Opportunistic page largification
Latching linear solenoid