Resources Contact Us Home
Clock tree topology

Image Number 3 for United States Patent #6353352.

A clock tree topology distributes a clock signal from a single input terminal 400 to three terminals 421-423 with an equal phase delay. The topology includes four lines 401-404 connected together at a first end 450 with adjacent lines forming right angles. A second end of the line 404 forms the clock signal input terminal 400. A second end of the remaining lines 401-403 are connected to first ends of lines 411-413. Second ends of the lines 411-413 form the terminals 421-423. A right angle is formed between each of the lines 401-403 and the respective one of the lines 411-413 to which it connects.

  Recently Added Patents
Fixing device, fixing device control method, and image forming apparatus
Watch dial
Systems and methods for dissipating an electric charge while insulating a structure
Switchable memory diodes based on ferroelectric/conjugated polymer heterostructures and/or their composites
Method and apparatus for an active low power mode of a portable computing device
Method and device for managing subscriber connection
Estimating travel time
  Randomly Featured Patents
Cooking device having a sensor responsive to an indicia for executing a cooking program
Process for lithium mono- and diorganylborohydrides
Low capacitance X-ray radiation detector
Plasma display panel having comb shaped electrode with teeth of specific pitch
Method for fabricating a capacitor
CMOS semiconductor device with (LDD) NMOS and single drain PMOS
Pelletizing die for a pelletizer
HMG-COA reductase inhibitors
Phosphoric acid compounds as co-stabilizers for Me(II)-carboxylates and/or Me(II)-phenolates in PVC