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Surface voltage sustaining structure for semiconductor devices having floating voltage terminal










Image Number 5 for United States Patent #6310365.

A surface voltage sustaining structure for semiconductor device which includes at least one high-side high-voltage device, comprises at least two surface voltage sustaining regions, wherein a first surface voltage sustaining region is for sustaining a voltage drop from a high voltage terminal of the high-side high-voltage device to a floating voltage terminal of the high-side high-voltage device, and a second surface voltage sustaining region is for sustaining a voltage drop from said high voltage terminal or from said floating voltage terminal to the substrate. The potential of the floating-voltage terminal of the high-side high-voltage device can vary (float) from the potential of the substrate up to the potential of the high voltage terminal. By means of the present invention, not only a high-side high-voltage device but also a low-side high-voltage device with a high voltage terminal having potential being the same as the floating voltage terminal and a low voltage terminal having potential being the same as the potential of the substrate, and integrated circuit devices with common terminals having a potential being the same as the floating voltage terminal, as well as integrated circuit devices with common terminals having a potential being the same as the substrate can be implemented simultaneously on a single chip without using dielectric isolation technique or p-n junction isolation technique. The technique of the present invention is technologically compatible to the CMOS or BiCMOS technique.








 
 
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