Image Number 2 for United States Patent #6304931.
In a bus control system for generating a series of access requests from an access requesting unit, such as a CPU connected to a common bus including a data bus or an address bus, to a specific access request responding unit, the specific access request responding unit includes a next-address enable signal generating unit for sending a next-address enable signal which represents that a next address can be received, to the access requesting unit before data is transferred or inputted, in accordance with an address representing the access request from the access requesting unit when a read operation or a write operation is executed. Preferably, the access requesting unit includes a next-address enable signal receiving unit for receiving the next-address enable signal from the specific access request responding unit and for sending the next address to the specific access request responding unit. On the other hand, a bus control method executed by using the bus control system, having the construction described above, is disclosed.
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