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Serial device compaction for improving integrated circuit layouts

Image Number 17 for United States Patent #6297668.

Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion. Adding complex-gates to a circuit while using asymmetric gates for smaller layouts achieves additional functionality. One component of the clock, along with the master drive circuit, is used to drive the slave latch of a flip-flop to avoid inserting additional gates into the logic of the fast output path. Reset and set circuitry is designed to be outside the critical path of the clock, and outside the slave latch, to provide rapid Q output response time to the clock and D inputs.

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