Image Number 17 for United States Patent #6294404.
A semiconductor integrated circuit according to the present invention comprises a synchronous SRAM, a signal generation circuit generating a chip selection signal, a clock signal etc. supplied to the synchronous SRAM, a voltage set circuit setting the voltage of a system power supply line and a controller controlling the signal generation circuit and the voltage set circuit. When setting the synchronous SRAM in a power down mode, the chip selection signal is set in a nonselective state and the power supply voltage of the system power supply line is stepped down to a standby potential. Thus, the synchronous SRAM enters a standby state having extremely low power consumption.