Resources Contact Us Home
Locally folded split level bitline wiring

Image Number 6 for United States Patent #6291335.

A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.

  Recently Added Patents
Presenting a link to a user
Systems and methods for optimizing capital structure of a financial institution
Model matching for trace link generation
Maize variety hybrid X13A495
Method of operating an election ballot printing system
Method and system for fail-safe call survival
Methods and apparatus for deactivating internal constraint curves when inflating an N-sided patch
  Randomly Featured Patents
Neutron dosimetry
Electronic parking meter system
White electrosensitive paper
Animal ear tag shield
Source address selection scheme suitable for multi-home environment
Tricycle kick board
System and methods for automatically accessing a web site on behalf of a client
Ball bar apparatus for calibrating a machine
Glue gun
Clip for use with a pacifier