Resources Contact Us Home
Locally folded split level bitline wiring

Image Number 4 for United States Patent #6291335.

A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.

  Recently Added Patents
Gas cap removal tool
Flame-protected impact-modified polycarbonate compositions
Haworthia plant named `AMSTERDAM`
Novelty snacks and method of manufacture of same
Spray drying vancomycin
Method for programming non-volatile memory device and apparatuses performing the method
Liquid low temperature injection molding process
  Randomly Featured Patents
Image-forming method and image-forming apparatus using the same
Cementing compositions and the application of such compositions to cementing oil or analogous wells
Quick attaching and detaching nut
Electrical interconnect system and method for integrating a bussed electrical distribution center with a printed circuit board
Water flush toilet bowl and a cast molding apparatus thereof
Ergonomic notebook stand
Absorbing article
Self-oscillating modulator and method for adjusting a self-oscillating modulator
Global localization by fast image matching
Sheet conveyor mechanism