Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Structure and method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel










Image Number 3 for United States Patent #6285061.

A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source/drain junction under the gate electrode but does not increase substantially the junction capacitance under the source/drain contacts, thereby improving punch-through characteristic while maintaining device performance.








 
 
  Recently Added Patents
Systems and methods for assigning a template to an existing network configuration
Expandable mobile device
Systems and/or methods for determining item serial number structure and intelligence
Petunia plant named `Bartpet001`
Electrophotographic photoreceptor, image-forming apparatus, and electrophotographic cartridge
Novelty snacks and method of manufacture of same
Algorithm for color corrected analog dimming in multi-color LED system
  Randomly Featured Patents
Surface covering articles
Tipless footstool
Method of making and polymer of heat resistant polyester using diglycidilarylimidazolones, and diglycidilalkyl ureas
Integrated light transfer structure for providing halo and end illumination for a control switch assembly
Jelly tube construction and method of waterproofing cable
Carbon security system for credit card sales
Lid for storage container
LED array printhead and method of adjusting light luminance of same
Hurricane damage recording camera system
Field emission type display