Resources Contact Us Home
Structure and method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel

Image Number 3 for United States Patent #6285061.

A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source/drain junction under the gate electrode but does not increase substantially the junction capacitance under the source/drain contacts, thereby improving punch-through characteristic while maintaining device performance.

  Recently Added Patents
Dynamic association and disassociation of threads to device functions based on requestor identification
Character input device and program for displaying next word candidates based on the candidates' usage history
Method and system for simulating superimposition of a non-linearly stretchable object upon a base object using representative images
Electronic package with fluid flow barriers
Motor control system, motor control device, and brushless motor
Liquid crystal display device
  Randomly Featured Patents
XML-based graphical user interface application development toolkit
Fabric structure with stand-off design
Chalk adhesion polymer composition and method of preparation
Gas separation membrane
Fuzzy computer
High voltage semiconductor devices and methods of forming the same
Fluid and air infusion device
Process for preparing cirramycin A.sub.1
Method of making a thin-walled bearing bushing