Image Number 3 for United States Patent #6285061.
A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source/drain junction under the gate electrode but does not increase substantially the junction capacitance under the source/drain contacts, thereby improving punch-through characteristic while maintaining device performance.
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