Resources Contact Us Home
Structure and method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel

Image Number 3 for United States Patent #6285061.

A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source/drain junction under the gate electrode but does not increase substantially the junction capacitance under the source/drain contacts, thereby improving punch-through characteristic while maintaining device performance.

  Recently Added Patents
Nonvolatile semiconductor memory device
Method for spore detection
Liquid crystal display wherein the data lines covered by each pixel electrode are supplied with data signals of opposite polarities
Active matrix substrate, method for manufacturing same, and liquid crystal display apparatus
Semiconductor device element formed on SOI substrate comprising a hollow region, and having capacitors in an electric field alleviation region
Fuel cell module
Sensing during magnetic resonance imaging
  Randomly Featured Patents
Apparatus and method for coverting cinematic images to video signals
Pumping apparatus
Method of enhancing the wettability of boron nitride for use as an electrochemical cell separator
Belt mower
Magnetic head positioner for magnetic disk apparatus which can prevent mechanical shock
Projectile launching apparatus
Synchronous memory device having advanced data align circuit
Relocation device
Method of upgrading optical node, and an optical node apparatus
Use of ammonium formate as a hydrogen transfer reagent for reduction of chiral nitro compounds with retention of configuration