Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Structure and method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel










Image Number 3 for United States Patent #6285061.

A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source/drain junction under the gate electrode but does not increase substantially the junction capacitance under the source/drain contacts, thereby improving punch-through characteristic while maintaining device performance.








 
 
  Recently Added Patents
SMS transport resource control
Predictive time entry for workforce management systems
Modulators of cystic fibrosis transmembrane conductance regulator
High-resolution, active reflector radio frequency ranging system
Method and system for distributing load by redirecting traffic
System and method for broadcasting rich media to devices over multiple carriers
Philanthropy management apparatus, system, and methods of use and doing business
  Randomly Featured Patents
Card for retaining items therein
16-METHYLENE-PROSTAGLANDIN COMPOUNDS
System and method for providing synchronized moving objects in an ornamental display
Frequency agile TDMA communications system
Vehicle frame construction for buggies with riding saddles
Display control of classified content based on flexible interface e-paper conformation
PLIF opposing wedge ramp
.beta.-secretase antibody
Mobile telephone intrasystem and intersystem enhanced handoff method and apparatus for limiting trunk switching connections
Headphones