Image Number 2 for United States Patent #6277757.
A method for fabricating funnel-shaped vias in semiconductor devices with an improved profile amelioration of the sharp angles at the onset of the via and at the intersection between the wet etch section (i.e., the bowl-shaped section) and the dry etch section (i.e., the straight section). The method includes the following main steps: (1) using PECVD to deposit a base dielectric layer on a wafer; (2) depositing a bottom dielectric layer on the base dielectric layer, the bottom dielectric layer having a first predetermined etch removal rate; (3) depositing at least one profile modifying dielectric layer on the bottom dielectric layer; (4) depositing a top dielectric layer on top of the at least one profile modifying dielectric layer, the top dielectric layer has a second predetermined etch removal rate, wherein the second predetermined etch removal rate is higher than the first predetermined etch removal rate; (5) forming a photoresist layer on the top dielectric layer, the photoresist layer containing an opening so as to allow a via to be formed through the multiplicity of dielectric layers; (6) using a simultaneous wet-and-dry etching process to form a funnel-shaped via in the multiplicity of dielectric layers. The dielectric layer material is selected such that its etch removal rate can be adjusted by adjusting one of the PECVD parameters.
|
