Image Number 3 for United States Patent #6265272.
A fabrication process of forming a semiconductor device with elevated source/drain regions on a substrate is disclosed. The elevated portion of the source/drain regions is provided as a reactant for a later metallization process, thereby preventing the consumption of too much silicon contained in the source/drain regions. First, an elevated silicon layer is formed on portions of a substrate for forming source/drain regions of a semiconductor device. Next, a gate dielectric layer and a gate electrode layer are formed on the elevated silicon layer successively to construct a gate structure. Then, a lightly doped ion implantation process, a process of forming a sidewall spacer and a heavily doped ion implantation process are performed successively. Thus, the elevated silicon layer can be used as a reactant while performing a self-aligned silicidization process.