Image Number 5 for United States Patent #6259648.
A pseudo dual port memory is constructed using a zero bus turnaround random access memory (RAM) wherein data words stored in the RAM each make up a plurality of data words for the pseudo dual port memory. Words written to the dual port memory are accumulated to assemble a single RAM word which is written into an addressed location within the RAM. Words read from the RAM correspondingly make up a plurality of data words for the dual port memory and are stored and multiplexed out as individual words. In the illustrated embodiment, each RAM word comprises two dual port memory words; however, other multiples, preferably powers of 2, can be used in the present invention such that each RAM word can comprise 4, 8, 16, etc. dual port memory words.