Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Programmable multi-standard I/O architecture for FPGAS










Image Number 4 for United States Patent #6242943.

The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards








 
 
  Recently Added Patents
Moving picture decoding device and moving picture decoding method
Partial response decision feedback equalizer with distributed control
High gradient lens for charged particle beam
Pre-distortion architecture for compensating non-linear effects
Bullet lens design for the dasal seeker
Flashlight
Managing wear leveling and garbage collection operations in a solid-state memory using linked lists
  Randomly Featured Patents
Distance-measuring system with in-range signalling for use with cameras, alarms, and the like
Pocess for increasing the resistance to corrosion and erosion of a vane of a rotating heat engine
ESD protection circuit for different power supplies
Mobile station apparatus, base station apparatus, management method in a mobile station apparatus, processing section and communication system
Matching and recommending relevant videos and media to individual search engine results
Canopy release mechanism
Device for creating a display of a variable, the value of which is digitally encoded
Lysobactin amides
Guide rail for electronic module supports
Vacuum compatible colleting spindle