Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Programmable multi-standard I/O architecture for FPGAS










Image Number 3 for United States Patent #6242943.

The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards








 
 
  Recently Added Patents
Case for a tablet computer
SIC semiconductor device and method for manufacturing the same
Motor assembly
Lower set insert with a lower ball seat for a downhole plug
System and methods for weak authentication data reinforcement
Jet pump and reactor
Hypallergenic mosaic antigens and methods of making same
  Randomly Featured Patents
Photostable filtering cosmetic composition
Gene delivery mediated by liposome-DNA complex with cleavable peg surface modification
Global positioning systems and inertial measuring unit ultratight coupling method
Internal combustion engine utilizing internal boost
Rapid leak detection system
Game machine door
Automatic device for the disinfection of W.C. bowls and seats
Method and apparatus to test an isochronous data transport
Gym bench towel
Flying apparatus