Resources Contact Us Home
Programmable multi-standard I/O architecture for FPGAS

Image Number 3 for United States Patent #6242943.

The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards

  Recently Added Patents
Bessel beam plane illumination microscope
System and method for oscillator frequency control
Enhancement of semiconducting photovoltaic absorbers by the addition of alkali salts through solution coating techniques
Pharmaceutical composition for treating CAPRIN-1 expressing cancer
Device, system, and method for logging near field communications tag interactions
Mobile device mode control based on dual mapping of availability (presence) information
Barrier layers comprising Ni-inclusive ternary alloys, coated articles including barrier layers, and methods of making the same
  Randomly Featured Patents
Apparatus and method for reducing current noise
Adjustable and recoverable vertical assembly
Copper alloys for electrical and electronic parts
Method of dynamically pre-fastening a disposable absorbent article having a slot-and-tab fastening system
Defects detection
Channel efficiency based packet scheduling for interactive data in cellular networks
Miticidal method
Prevention and treatment of ocular side effects with a cyclosporin
Spoken language understanding that incorporates prior knowledge into boosting
Organic light emitting display with compensation for transistor threshold variation