Resources Contact Us Home
Programmable multi-standard I/O architecture for FPGAS

Image Number 2 for United States Patent #6242943.

The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards

  Recently Added Patents
Heat shield and laminated glass
Antibodies to CCR2
Over the counter medicinal container with surface ornamentation
Method for the analysis of solid objects
Stable pharmaceutical composition and methods of using same
Package for a medicinal product
Frame syncrhonization in orthogonal frequency-division multiplexing systems
  Randomly Featured Patents
Scissors handle
Molded knee pad
Prosthetic vertebral body
Methods and systems for facilitating stimulation of one or more stimulation sites
Retainer for roller bearing and method for manufacturing the same
Steam generator heat exchanger for cooking equipment
System for biotin synthesis
System for creating a patterned polarization compensator
[(3-heteroaryl-1-pyrrolidinyl) alkoxy]-3,4-dihydro-1(2H)-naphthalenones and related compounds and their therapeutic utility
Image recording apparatus and head driving control apparatus