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Wiring substrate and manufacturing method thereof

Image Number 18 for United States Patent #6177635.

A coating insulator layer has plural rows of through holes disposed longitudinally in the coating insulator layer. A plurality of conductors are disposed in parallel with one another longitudinally in the coating insulator layer. Each conductor does not interfere with the through holes. Plural rows of locking projections are longitudinally formed on a face of the coating insulator layer. The locking projection has a construction to engage with the through hole. Thus, when a couple of the wiring substrates are layered, some of the locking projections formed on one of the wiring substrates are aligned to be engaged with some relative through holes of the other wiring substrate, allowing a sure lamination of the wiring substrates. The locking projections are disposed in regular intervals and the through holes are spaced in the same regular intervals. Another wiring substrate is enough flexible to be arranged along a structural wall for wiring. The wiring substrate has a stiffener means disposed in the insulator layer. The stiffener means is positioned not to interfere with the conductors and provides enough stiffness to keep the wiring substrate in a desired shape. The stiffener means has a larger strength than the insulator layer in bending strength and the stiffener means is disposed parallel with the longitudinal direction of the conductors. The wiring substrate has a plurality of through holes which each can be engageable with a locking projection provided on the structural wall.

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