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Device and process for detecting errors in an integrated circuit comprising a parallel-serial port

Image Number 2 for United States Patent #6173423.

A device for detecting errors with an integrated self-check, on an integrated circuit comprising a serial link control function for constituting an input-output port (109) between a parallel bus (L2CB, C2LB) and a serial link. The integrated circuit comprises a serializer circuit (109.sub.T) on output and a deserializer circuit (109.sub.R) on input. An insertion buffer I-sb has each of its outputs connected to one input of an exclusive OR operation with two inputs. The second input of the exclusive OR operation receives a piece of information (o-s) to be transmitted in order to constitute, with the insertion information issuing from the insertion buffer, a piece of substitute information. An additional buffer (I-tb) makes it possible to compare the sequence supplied as output from the exclusive OR with a sequence stored in the additional buffer (I-tb) in order to validate the transmission of the substitute sequence. A history buffer (HIB) stores characters received from the deserializer and makes it possible to diagnose the error.

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