Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
MONOS flash memory for multi-level logic and method thereof










Image Number 5 for United States Patent #6166410.

The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.








 
 
  Recently Added Patents
Package for a medicinal product
Cell reselection and handover with multimedia broadcast/multicast service
Multiple-frequency inversion method and control apparatus for internal combustion engine driven generator
Methods for testing OData services
Control device of hybrid vehicle
Method for conductivity control of (Al,In,Ga,B)N
Self cleaning rake
  Randomly Featured Patents
Color format conversion in a parallel processor
Anode-fitting assembly
Use of pairs of leucine zipper peptides in immunoassay methods
Circuit and method for wrap-around sign extension for signed numbers using replacement of most significant bit
Astaxanthin-producing yeast cells, methods for their preparation and their use
Promotional route truck assembly
Scanning devices
Electrolytic solution for electric double layer capacitor and electric double layer capacitor
Method for the purification of dinitroanilines
Probe, probe set, probe carrier, and testing method