Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
MONOS flash memory for multi-level logic and method thereof










Image Number 11 for United States Patent #6166410.

The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.








 
 
  Recently Added Patents
Systems and methods for controlling phasing of advancing substrates in absorbent article converting lines
Systems and methods for generating a hybrid text string from two or more text strings generated by multiple automated speech recognition systems
Pyroelectric detector, pyroelectric detection device, and electronic instrument
Method and apparatus for transcoding and transrating in distributed video systems
Dynamic rebasing of persisted time information
Image forming apparatus with enhanced display of guidance information
Flexible organic light emitting device and manufacturing method thereof
  Randomly Featured Patents
Round baler having interlock mechanism for assuring post discharge actuation of ejected bale repositioner
Multi-processor element provided with hardware for software debugging
Asymmetric data communications system
Stably tethered structures of defined compositions with multiple functions or binding specificities
Filtering unit and method of sealing same
Monoclonal antibody-based immunoassay for cyclic DNA adducts resulting from exposure to crotonaldehyde or acrolein
Miniaturized reaction apparatus
Apparatus and process for sensing fluoro species in semiconductor processing systems
Oxidation-leaching of chalcopyrite
Laser ablation electrospray ionization (LAESI) for atmospheric pressure, in vivo, and imaging mass spectrometry