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Fast linear tag validation unit for use in microprocessor










Image Number 8 for United States Patent #6157986.

A linearly addressed cache capable of fast linear tag validation after a context switch or a translation lookaside buffer (TLB) flush. The cache is configured to validate multiple linear address tags to improve performance in systems which experience frequent context switches or TLB flushes. The cache comprises: a data array configured to store a plurality of cache lines, a linear tag array, a physical tag array, and a TLB. Each array is configured to receive a portion of a requested address. Each linear tag stored in the linear tag array corresponds to one cache line stored within the data array. Each physical tag stored in the physical tag array also corresponds to one cache line stored within the data array. The TLB is configured to store linear to physical address translations, while the linear tag array is configured to store status information for each linear tag. The status information comprises a linear tag valid bit and an enable compare bit. The linear tag array is configured as a content addressable memory and is configured to perform a parallel comparison of a first portion of the requested address with each of the plurality of stored linear tags. If one of the tags match, the linear tag array sets the corresponding valid bits if the corresponding enable compare bits are set. The linear tag array may also be configured to clear the enable compare bits in parallel.








 
 
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