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Circuit for controlling writing data into memory and allowing concurrent reset generation and writing data operation

Image Number 3 for United States Patent #6119211.

There is provided a circuit for controlling writing data into an address of a memory, the data and address being transmitted from a central processing unit, the circuit (a) latching address and data transmitted from the central processing unit, (b) storing a first signal transmitted from the central processing unit, (c) writing latched data into a latched address of the memory by a second signal associated with the first signal, and (d) invalidating the second signal after a period of time necessary for writing data into the address has passed. The above mentioned circuit makes sure that writing data into a memory can be completed without destruction of the data, even if a reset factor is generated while data is being written into a memory. In addition, reset timing for an entire device in which the above mentioned circuit is contained is not out of phase, ensuring prevention of malfunction of the device.

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