Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method and apparatus for logic synchronization










Image Number 12 for United States Patent #6118304.

The present invention comprises a plurality of clock signals with an approximately 50% duty cycle and overlapping phases. The phases of the plurality of clocks are such that the phase of an individual clock signal overlaps the phase of an earlier clock signal by an amount equal to the overlap of the phase of the next clock signal. The present invention further comprises a plurality of clocked precharge (CP) logic gates coupled in series. An individual CP logic gate couples to an individual clock signal though the CP logic gate's evaluate device. For the data flow through the individual CP logic gate, the logic gate receives its data input from an earlier CP logic gate in the series and passes to the next CP logic gate in the series. The earlier CP logic gate couples to an earlier phase clock signal, and the next CP logic gate couples to the next phase clock signal. The present invention additionally provides that a logic gate may only feed another logic circuit in a feed back loop or a feed forward loop that uses the next phase clock signal.








 
 
  Recently Added Patents
Table base
Systems for usage based rate limiting over a shared data link
Vending machine
Mechanical and moisture protection apparatus for electronic devices
Digital broadcasting system and method of processing data
Monitoring heap in real-time by a mobile agent to assess performance of virtual machine
Cooking tray
  Randomly Featured Patents
Vacuum cleaner locking system
Automatic sawmill method and apparatus
Flavonoid complexes
Magnetic utility lamp
Eccentric nozzle for powder filling systems
Heater assembly and heater element therefor
Photoerasable paint and method for using photoerasable paint
Conversion of olefins by catalytic distillation
Noise and offset voltage-compensated electromagnetic flowmeter
Method of making memory devices