Image Number 2 for United States Patent #6091632.
A plurality of blocks of memory cell transistors are formed on the respective isolated wells. In a write stage, a predetermined write-stage well voltage is applied to the well of a selected block including the memory cell transistors to be subjected to a write operation, a bias voltage is applied to the well of each of the remaining, non-selected blocks to increase a threshold voltage of the memory cell transistors of each non-selected block, in comparison with a threshold voltage determined by the predetermined write-stage well voltage, and a voltage is applied to the control gates of the memory cell transistors of each non-selected block to reduce a difference between a potential of the floating gate of each memory cell transistor of each non-selected block and a write-stage drain voltage applied to the drain of the memory cell transistor through the associated bit line such that a source-drain leak current of each memory cell transistor in the non-selected blocks falls in a permissible range.
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