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Method and apparatus for increasing the time available for refresh for 1-t SRAM compatible devices










Image Number 10 for United States Patent #6075740.

A memory system including a DRAM array, a read buffer, a write buffer and an input/output (I/O) interface. The read buffer and write buffer are coupled between the DRAM array and the I/O interface. When an external transaction involves multiple pieces of data in consecutive address locations, such as a burst access, parallel operations are performed in the DRAM array and the I/O interface. In a burst read transaction, all the data in the burst transaction is pre-fetched from the DRAM memory into the read buffer in one memory cycle. After the read data has been pre-fetched, the DRAM array is available for a refresh operation. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/O interface. In a burst write transaction, multiple burst write data values are written to the write buffer over multiple I/O cycles. This burst write data is not retired to the DRAM array until the next write transaction. At this time, all of the burst write data is simultaneously retired to the DRAM array. As a result, the DRAM array is only engaged in the burst write transaction for one memory cycle. Because the DRAM array is not engaged in the transfer of the new data values from the I/O interface to the write buffer, the DRAM array can be refreshed during one or more of the remaining three I/O cycles.








 
 
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