Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Apparatus for performing multiply-add operations on packed data










Image Number 12 for United States Patent #6035316.

A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first, second, third, and fourth multiplier, wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder coupled to the first and second multipliers, and second adder coupled to the third and fourth multipliers. A third storage area is coupled to the adders. The third storage area includes a first and second field for saving output of the first and second adders, respectively, as first and second data elements of a third packed data.








 
 
  Recently Added Patents
Method of manufacturing semiconductor device
Resonant oscillator with start up and shut down circuitry
Fast and compact circuit for bus inversion
Electronic device and control method therein
Laser processing method and apparatus
Lens module and method for manufacturing thereof
(-)-epigallocatechin gallate derivatives for inhibiting proteasome
  Randomly Featured Patents
3,4-dihydro-2H-1-benzopyran derivatives
Aqueous developable photosensitive polyurethane-methacrylate
Portable alarm system with sealed enclosure
Ram air steering system for a guided missile
Heat-developable photosensitive material and method of processing the same
Apparatus and method for managing random-directional scratches on hard disk
Dual fiber optical collimator
EGFR polymorphisms predict gender-related treatment
Perimeter skimming gutter with fluid level-responsive weir closure for weir skimming flow control
Water and method for storing silicon wafer