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Non-volatile semiconductor memory










Image Number 3 for United States Patent #5962890.

A non-volatile semiconductor memory in which a plurality of flash memory cells are arranged in a matrix, each flash memory cell including source and drain regions formed on a silicon substrate, a floating gate formed on at least a part of the source and drain regions with a dielectric film provided therebetween, and a control gate formed on the floating gate with a dielectric layer provided therebetween, wherein a writing operation is performed by applying a positive voltage to the drain region and a negative voltage to the control gate and extracting electrons from the floating gate to the drain region by an FN tunnel current, a common source line for connecting the source region of the flash memory cells includes a diffusion layer formed in the silicon substrate and a silicide formed on the diffusion layer, and impurity concentration of the source region and the common source line are set lower than the impurity concentration of the drain region.








 
 
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