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Non-volatile SRAM

Image Number 5 for United States Patent #5956269.

A method and devices are provided for producing a non-volatile SRAM, of the type composed of two back-to-back, cross-coupled, CMOS inverters, each with a PMOS and an NMOS and respective outputs Q and Q.about. connected therebetween, even when the cell is completely symmetrical, by creating a stable condition wherein Q.noteq.Q.about. through rendering the threshold voltages of the NMOS devices different. The threshold voltages of the NMOSs are made different by using hot electron injection. The hot electron effect is produced by meeting the conditions, that 1) one of the NMOSs must be in saturation condition, i.e., V.sub.DS .gtoreq.V.sub.GS, where V.sub.DS is the drain to source voltage, V.sub.GS is the gate to source voltage, and the threshold voltage, of the NMOS, and 2) V.sub.DS must be large enough, typically about 7 V, depending on the fabrication process. To achieve these conditions, for example, firstly a regular write function is performed on the SRAM so that the cell will have a predetermined condition, i.e., a high, low or low, high value. A negative voltage pulse is then applied to the inverter with the high output value to put its NMOS in a saturation state. This results in producing hot electrons that are stored in the gate oxide of the NMOS, thus making the threshold voltage of the two NMOS devices unbalanced, i.e., V.sub.th1 .notident.V.sub.th2, and achieving the function of hard memory.

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