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Semiconductor memory device capable of driving the data bus sense amplifier in both read and write modes










Image Number 2 for United States Patent #5914909.

A semiconductor memory device having a data bus sense amplifier driving part for driving a data bus sense amplifier in a read mode in response to a global data bus line selection signal and a data bus line selection signal, a write driver driving part for driving a write driver in a write mode in response to the data bus line selection signal and a write bus line driver signal generation signal, and a logic gate for logically combining output signals from the data bus sense amplifier driving part and write driver driving part to generate a signal to drive the data bus sense amplifier in the write and read modes. The data bus sense amplifier is driven even in the write mode to change the previous data latched by a latch circuit. Therefore, in the case where data stored in a cell in the write mode is outputted in the read mode by a corresponding address and different data is then stored in the same cell, the different data can normally be read directly by the corresponding address without performing a read or write operation according to a different address.








 
 
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